Small-Signal Models

Small-Signal Models
   There are two small-signal circuit models which are commonly used to analyze JFET circuits.
These are the hybrid-π model and the T model. The two models are equivalent and give identical
results. They are described below.

Hybrid-π Model
   Let the drain current and each voltage be written as the sum of a dc component and a small-signal
ac component as follows:
             iD = ID + id
             vGS = VGS + vgs
             vDS = VDS + vds

If the ac components are sufficiently small, we can write


where the derivatives are evaluated at the dc bias values. Let us define

The drain current can thus be written

id = i'd + vds/r0

where

i'd = i's = gmvgs

The gate current is given by ig = i's −i'd = 0. The small-signal circuit which models these equations is given in Fig. 5(a). This is called the hybrid-π model. The resistor rd is the parasitic resistance in series with the drain contact. It has a typical value of 50 to 100 Ω. Often it is neglected in calculations. This is done in the following. It is simple to account for rd in any equation by adding it to the external drain load resistance.



T Model
The T model of the JFET is shown in Fig. 5(b). The resistor r0 is given by Eq. (15). The resistor rs is given by

where gm is the transconductance defined in Eq. (14). The currents are given by


The currents are the same as for the hybrid-π model. Therefore, the two models are equivalent.

Small-Signal Equivalent Circuits

   Several equivalent circuits are derived below which facilitate writing small-signal low-frequency equations for the JFET. We assume that the circuits external to the device can be represented by Thévenin equivalent circuits. The Norton eqivalent circuit seen looking into the drain and the Thévenin equivalent circuit seen looking into the source are derived. Several examples are given which illustrate use of the equivalent circuits.

Simplified T Model

   Figure 6(a) shows the JFET T model with a Thévenin source in series with the gate. We wish to solve for the equivalent circuit in which the source i'd connects from the drain node to ground rather than from the drain node to the gate node. We call this the simplified T model. Aside for the subscripts, the T model in Fig. 5(b) is identical to the T model for the BJT with rx = 0.
Therefore, the simplified T model for the JFET must be of the same form as the simplified T model for the BJT. Because ig = 0, the effective current gains of the JFET are α = 1 and β = ∞. The simplified T model is shown in Fig. 6(b), where i'd and rs are given by


Norton Drain Circuit

   The Norton equivalent circuit seen looking into the drain can be used to solve for the response of the common-source and common-gate stages. Fig. 7(a) shows the JFET with Thévenin sources connected to its gate and source. The Norton drain circuit follows directly from the BJT Norton collector circuit with appropriate changes in subscripts and the substitutions α = 1, and β = ∞, and rx = 0. The circuit is given in Fig. 7(b), where id(sc) and rid are given by
                                   id(sc) = Gmg.Vtg − Gms.Vts



The two transconductances Gmg and Gms are given by



For the case r0 >> Rts and r0 >> rs, we can write
                        id(sc) = Gm (vtg − vts)

where

The value of id(sc) calculated with this approximation is simply the value of i's calculated with r0 considered to be an open circuit. The term "r0 approximations" is used in the following when r0 is neglected in calculating id(sc) but not neglected in calculating rid.

Thévenin Source Circuit

   The Thévenin equivalent circuit seen looking into the source is useful in calculating the response of common-drain stages. Fig. 8(a) shows the JFET symbol with a Thévenin source connected to the gate. The resistor Rtd represents the external load resistance in series with the drain. The Thévenin source seen looking into the source follows directly from the Thévenin emitter circuit for the BJT with appropriate subscript changes and the substitutions α = 1, β = ∞, and rx = 0. The circuit is shown in Fig. 8(b), where vs(oc) and ris are given by

When Rtd = 0, note that ris = rs//r0.

Summary of Models

Figure 9 summarizes the four equivalent circuits derived above.




Nombre: María José Nieto Cárdenas
Asignatura: EES
Fuente: http://users.ece.gatech.edu/mleach/ece3050/notes/jfet/thejfet.pdf

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