domingo, 30 de mayo de 2010

CONMUTADOR

   Es un dispositivo eléctrico o electrónico que permite modificar el camino que deben seguir los electrones. Son típicos los manuales, como los utilizados en las viviendas y en dispositivos eléctricos, y los que poseen algunos componentes eléctricos o electrónicos como el relé. Se asemejan a los interruptores en su forma exterior, pero los conmutadores a la vez que desconectan un circuito, conectan otro. Seguidamente se describen los tipos de conmutadores más usuales.

Conmutador alternativo

También denominado conmutador de hotel o de dos direcciones sin punto neutro. Se utilizan siempre que haya que activar o desactivar un dispositivo desde dos lugares diferentes, como por ejemplo una lámpara. En las viviendas es típico encontrarlos en los salones o pasillos.

Conmutador de cruce

Conocido también como conmutador inversor, este elemento no se instala nunca aislado, siempre han de ir acompañado por los conmutadores alternativos. Sirven por ejemplo para poder encender o apagar una lámpara desde tres puntos distintos, para lo cual se emplean dos conmutadores alternativos y un conmutador de cruce según se aprecia en la figura. Si el número de puntos de encendido/apagado es mayor de tres, se intercalarán tantos conmutadores de cruce como puntos se tengan, siempre entre dos conmutadores alternativos.

                      Márquez M. Wiston J.
                            CI. 16745566.
                          Asignatura CAF.


CMOS

CMOS (del inglés complementary metal-oxide-semiconductor, "estructuras semiconductor-óxido-metal complementarias") es una de las familias lógicas empleadas en la fabricación de circuitos integrados (chips). Su principal característica consiste en la utilización conjunta de transistores de tipo pMOS y tipo nMOS configurados de tal forma que, en estado de reposo, el consumo de energía es únicamente el debido a las corrientes parásitas.
En la actualidad, la mayoría de los circuitos integrados que se fabrican utilizan la tecnología CMOS. Esto incluye microprocesadores memorias, DSPs y muchos otros tipos de chips digitales.
  • Cuando la entrada es 1, el transistor nMOS está en estado de conducción. Al estar su fuente conectada a tierra (0), el valor 0 se propaga al drenador y por tanto a la salida de la puerta lógica. El transistor pMOS, por el contrario, está en estado de no conducción
  • Cuando la entrada es 0, el transistor pMOS está en estado de conducción. Al estar su fuente conectada a la alimentación (1), el valor 1 se propaga al drenador y por tanto a la salida de la puerta lógica. El transistor nMOS, por el contrario, está en estado de no conducción.
Otra de las características importantes de los circuitos CMOS es que son regenerativos: una señal degradada que acometa una puerta lógica CMOS se verá restaurada a su valor lógico inicial 0 o 1, siempre y cuando aún esté dentro de los márgenes de ruido que el circuito pueda tolerar.  
                        Márquez M. Wiston J.
                               CI. 16745566.
                            Asignatura: CAF.

DNAFET

DNAFET

 DNA field-effect transistor, es un transistor de efecto de campo (o FET) que utiliza el efecto de campo generado por las cargas parciales de las moléculas de ADN para actuar como un biosensor. La estructura de los DNAFET es similar a la de los MOSFET, con la excepción de la estructura de la puerta que, en los DNAFET, es reemplazada por una capa de moléculas de cadenas sencillas de ADN que actúan como receptores de superficie. Cuando las cadenas del ADN complementario hibridan los receptores, cambia la distribución de la carga cerca de la superficie, lo que modula el transporte en curso a través del transductor semiconductor.
Se pueden usar chips de DNAFET para detectar polimorfismos de nucleótido simple (que pueden causar varias enfermedades hereditarias) y para secuenciación de ADN. Su principal ventaja en comparación con los métodos de detección óptica de uso común actualmente, es que no requieren el marcaje de moléculas. Además, trabajan continuamente y (casi) en tiempo real. Los DNAFET son altamente selectivos, ya que sólo uniones específicas modulan el transporte de carga.

Es un biosensor, un instrumento para la medición de parámetros biológicos o químicos. Suele combinar un componente de naturaleza biológica y otro físico-químico.
Se compone de tres partes:
  • El sensor biológico: Puede ser un tejido, un cultivo de microorganismos, enzimas, anticuerpos, cadenas de ácidos nucléicos, etc. El sensor puede ser tomado de la naturaleza o ser un producto de la biología sintética.
  • El transductor: Acopla los otros dos elementos y traduce la señal emitida por el sensor.
  • El detector: Puede ser óptico, piezoeléctrico, térmico, magnético, etc.
                 Márquez M. Wiston J.
                    CI. 16745566.
                 Asignatura: CAF.

IGBT

El IGBT es adecuado para velocidades de conmutación de hasta 20 KHz y ha sustituido al BJT en muchas aplicaciones. Es usado en aplicaciones de altas y medias energía como fuente conmutada, control de la tracción en motores y cocina de inducción. Grandes módulos de IGBT consisten en muchos dispositivos colocados en paralelo que pueden manejar altas corrientes del orden de cientos de amperios con voltajes de bloqueo de 6.000 voltios.
Se puede concebir el IGBT como un transistor Darlington híbrido. Tiene la capacidad de manejo de corriente de un bipolar pero no requiere de la corriente de base para mantenerse en conducción. Sin embargo las corrientes transitorias de conmutacion de la base pueden ser igualmente altas. En aplicaciones de electronica de potencia es intermedio entre los tiristores y los mosfet. Maneja más potencia que los segundos siendo más lento que ellos y lo inverso respecto a los primeros.



                      Márquez M. Wiston J.
                               CI. 16745566.
                            Asignatura: CAF.


TFT

TFT, siglas de Thin Film Transistor (en inglés: Transistor de Película Fina), es un tipo especial de transistor de efecto campo que se fabrica depositando finas películas de un semiconductor activo así como una capa de material dieléctrico y contactos metálicos sobre un sustrato de soporte. Un sustrato muy común es el cristal. Una de las primeras aplicaciones de los TFTs son las pantalla   de cristal líquido.
Los TFTs se pueden fabricar con una gran variedad de materiales semiconductores. El más común es el silicio. Las características del TFT basado en el silicio depende de su estado cristalino. Esto es, que la capa de semiconductor puede ser silicio amorfo, silicio microcristalino o puede haber sido templado en un polisilicio. Otros materiales que pueden ser usados como semiconductores en TFTs son el cadmio selenio (CdSe) y óxidos de metal como el Óxido de Zinc. Los TFTs también pueden ser fabricados usando materiales orgánicos (Organic TFT u OTFT).
Usando semiconductores y electrodos transparentes, como el Indio-Óxido de Estaño (ITO), los dispositivos TF pueden hacerse completamente transparentes.


HEMT

5) HEMT
Los HEMT son Transistores tipo FET, en que se reemplaza el canal de conducción por una juntura en la que se unen dos materiales semiconductores con diferentes brechas entre las bandas de conducción y de valencia, lo que produce una capa muy delgada en la cual el nivel de Fermi esta un poco por sobre la banda de conducción, por otro lado los portadores quedan confinados a una capa tan angosta que se los puede describir como un gas de electrones de dos dimensiones. Por estas dos razones los portadores de carga adquieren una muy alta movilidad y una alta velocidad de saturación, habilitándolos para reaccionar a campos que varían a muy altas frecuencias, como también reduce muy significativamente el efecto de dispersión que los átomos de dopaje producen sobre los portadores de carga rediciendo en gran medida el ruido que este dispositivo emite.
Normalmente los dos materiales semiconductores tiene la misma estructura cristalina permitiendo un adecuado calce entre estas, esto con el objeto de evitar que los portadores queden atrapados en las discontinuidades que se podrían producir. Reduciendo su rendimiento.
Existe un tipo de HEMT en los cuales esto no se cumple, los pseudomorphic HEMT (PHEMT), en ellos se pone una capa extremadamente delgada de de unos de los materiales, tanto que esta se deforma para calzar con el otro material. Con esto se logran brechas de energía mucho más altas permitiendo un mejor rendimiento del transistor.
Otra forma de lograr lo anterior es la inserción de una capa muy delgada de adaptación entre los dos materiales de forma que esta se la encargada de unir las dos estructuras cristalinas, esto presenta una ventaje cuando la capa de adaptaciones esta construida con AlInAs, en este material la concentración de In es graduada de forma de calzar las estructuras cristalinas, entonces se tiene que una alta concentración de In produce alta ganancia y una baja concentración produce bajo ruido.

                    Márquez M. Wiston J.
                               CI. 16745566.
                            Asignatura: CAF.


JFET

Transistor de efecto de campo de unión es un dispositivo electrónico, esto es, un circuito que, según unos valores eléctricos de entrada, reacciona dando unos valores de salida. En el caso de los JFET, al ser transistores de efecto de campo eléctrico, estos valores de entrada son las tensiones eléctricas, en concreto la tensión entre los terminales S (fuente) y G (puerta), VGS. Según este valor, la salida del transistor presentará una curva característica que se simplifica definiendo en ella tres zonas con ecuaciones definidas: corte, óhmica y saturación.
Físicamente, un JFET de los denominados "canal P" está formado por una pastilla de semiconductor tipo P en cuyos extremos se sitúan dos patillas de salida (drenador y fuente) flanqueada por dos regiones con dopaje de tipo N en las que se conectan dos terminales conectados entre sí (puerta). Al aplicar una tensión positiva (en inversa) VGS entre puerta y fuente, las zonas N crean a su alrededor sendas zonas en las que el paso de electrones (corriente ID) queda cortado, llamadas zonas de exclusión. Cuando esta VGS sobrepasa un valor determinado, las zonas de exclusión se extienden hasta tal punto que el paso de electrones ID entre fuente y drenador queda completamente cortado. A ese valor de VGS se le denomina Vp. Para un JFET "canal N" las zonas p y n se invierten, y las VGS y Vp son positivas, cortándose la corriente para tensiones mayores que Vp.
Así, según el valor de VGS se definen dos primeras zonas; una activa para tensiones negativas mayores que Vp (puesto que Vp es también negativa) y una zona de corte para tensiones menores que Vp. Los distintos valores de la ID en función de la VGS vienen dados por una gráfica o ecuación denominada ecuación de entrada.
En la zona activa, al permitirse el paso de corriente, el transistor dará una salida en el circuito que viene definida por la propia ID y la tensión entre el drenador y la fuente VDS. A la gráfica o ecuación que relaciona estás dos variables se le denomina ecuación de salida, y en ella es donde se distinguen las dos zonas de funcionamiento de activa: óhmica y saturación.
Archivo:Esquema interno del transistor JFET.svg


                              Márquez M. Wiston J.
                                         CI. 16745566.
                                       Asignatura CAF.


MOSFET

3) Transistor MOSFET
Un transistor MOSFET consiste en un sustrato de material semiconductor dopado en el que, mediante técnicas de difusión de dopantes, se crean dos islas de tipo opuesto separadas por un área sobre la cual se hace crecer una capa de dieléctrico culminada por una capa de conductor. Los transistores MOSFET se dividen en dos tipos fundamentales dependiendo de cómo se haya realizado el dopaje:
  • Tipo nMOS: Sustrato de tipo p y difusiones de tipo n.
  • Tipo pMOS: Sustrato de tipo n y difusiones de tipo p.
Las áreas de difusión se denominan fuente(source) y drenador(drain), y el conductor entre ellos es la puerta(gate).
El transistor MOSFET tiene tres estados de funcionamiento:

Estado de corte

Cuando la tensión de la puerta es idéntica a la del sustrato, el MOSFET está en estado de no conducción: ninguna corriente fluye entre fuente y drenador aunque se aplique una diferencia de potencial entre ambos. También se llama mosfet a los aislados por juntura de dos componentes.

Conducción lineal

Al polarizarse la puerta con una tensión negativa (pMOS) o positiva (nMOS), se crea una región de deplexión en la región que separa la fuente y el drenador. Si esta tensión crece lo suficiente, aparecerán portadores minoritarios (electrones en pMOS, huecos en nMOS) en la región de deplexión que darán lugar a un canal de conducción. El transistor pasa entonces a estado de conducción, de modo que una diferencia de potencial entre fuente y drenador dará lugar a una corriente. El transistor se comporta como una resistencia controlada por la tensión de puerta.

Saturación

Cuando la tensión entre drenador y fuente supera cierto límite, el canal de conducción bajo la puerta sufre un estrangulamiento en las cercanías del drenador y desaparece. La corriente entre fuente y drenador no se interrumpe, ya que es debida al campo eléctrico entre ambos, pero se hace independiente de la diferencia de potencial entre ambos terminales.

Modelos matemáticos

  • Para un MOSFET de canal inducido tipo n en su región lineal:
I_{D (Act)} = K [(V_{GS} - V_T)V_{DS} - \frac{V_{DS}^2}{2} ]
donde K = \frac{b\mu_n\epsilon}{LW}en la que b es el ancho del canal, μn la movilidad de los electrones, ε es la permitividad eléctrica de la capa de óxido, L la longitud del canal y W el espesor de capa de óxido.
  • Cuando el transistor opera en la región de saturación, la fórmula pasa a ser la siguiente:
I_{D (Sat)} = \frac{K + 1}{K_0}(V_{GS}-V_{T})^2
Estas fórmulas son un modelo sencillo de funcionamiento de los transistores MOSFET, pero no tienen en cuenta un buen número de efectos de segundo orden, como por ejemplo:
  • Saturación de velocidad: La relación entre la tensión de puerta y la corriente de drenador no crece cuadráticamente en transistores de canal corto.
  • Efecto cuerpo: La tensión entre fuente y sustrato modifica la tensión umbral que da lugar al canal de conducción
  • Modulación de longitud de canal.

FET

2) Características del FET
Tiene una resistencia de entrada extremadamente alta (casi 100M).
No tiene un voltaje de unión cuando se utiliza Conmutador (Interruptor).
Hasta cierto punto inmune a la radiación.
Es menos ruidoso.
Puede operarse para proporcionar una mayor estabilidad térmica.


         Márquez M. Wiston J.
                      CI. 16745566.
        Asignatura CAF


Transistor de efecto de campo

Transistor de efecto de campo.

 

1) Definición:     El transistor de efecto campo (Field-Effect Transistor o FET, en inglés) es en realidad una familia de transistores que se basan en el campo eléctrico para controlar la conductividad de un "canal" en un material semiconductor. Los FET pueden plantearse como resistencias controladas por diferencia de potencial.
Tienen tres terminales, denominadas puerta (gate), drenador (drain) y fuente (source). La puerta es el terminal equivalente a la base del BJT. El transistor de efecto de campo se comporta como un interruptor controlado por tensión, donde el voltaje aplicado a la puerta permite hacer que fluya o no corriente entre drenador y fuente.

 


sábado, 29 de mayo de 2010

Common source

In electronics, a common-source amplifier is one of three basic single-stage field-effect transistor (FET) amplifier topologies, typically used as a voltage or transconductance amplifier. The easiest way to tell if a FET is common source, common drain, or common gate is to examine where the signal enters and leaves. The remaining terminal is what is known as "common". In this example, the signal enters the gate, and exits the drain. The only terminal remaining is the source. This is a common-source FET circuit. The analogous bipolar junction transistor circuit is the common-emitter amplifier.

The common-source (CS) amplifier may be viewed as a transconductance amplifier or as a voltage amplifier. (See classification of amplifiers). As a transconductance amplifier, the input voltage is seen as modulating the current going to the load. As a voltage amplifier, input voltage modulates the amount of current flowing through the FET, changing the voltage across the output resistance according to Ohm's law. However, the FET device's output resistance typically is not high enough for a reasonable transconductance amplifier (ideally infinite), nor low enough for a decent voltage amplifier (ideally zero). Another major drawback is the amplifier's limited high-frequency response. Therefore, in practice the output often is routed through either a voltage follower (common-drain or CD stage), or a current follower (common-gate or CG stage), to obtain more favorable output and frequency characteristics. The CS–CG combination is called a cascode amplifier.


Figure 1: Basic N-channel JFET common-source circuit (neglecting biasing details).


Figure 2: Basic N-channel JFET common-source circuit with source degeneration.
Characteristics
At low frequencies and using a simplified hybrid-pi model, the following small-signal characteristics can be derived.

Bandwidth
The bandwidth of the common-source amplifier tends to be low, due to high capacitance resulting from the Miller effect. The gate-drain capacitance is effectively multiplied by the factor , thus increasing the total input capacitance and lowering the overall bandwidth.

Figure 3 shows a MOSFET common-source amplifier with an active load. Figure 4 shows the corresponding small-signal circuit when a load resistor RL is added at the output node and a Thévenin driver of applied voltage VA and series resistance RA is added at the input node. The limitation on bandwidth in this circuit stems from the coupling of parasitic transistor capacitance Cgd between gate and drain and the series resistance of the source RA. (There are other parasitic capacitances, but they are neglected here as they have only a secondary effect on bandwidth.)

Using Miller's theorem, the circuit of Figure 4 is transformed to that of Figure 5, which shows the Miller capacitance CM on the input side of the circuit. The size of CM is decided by equating the current in the input circuit of Figure 5 through the Miller capacitance, say iM , which is:



to the current drawn from the input by capacitor Cgd in Figure 4, namely jωCgd vGD. These two currents are the same, making the two circuits have the same input behavior, provided the Miller capacitance is given by:


Usually the frequency dependence of the gain vD / vG is unimportant for frequencies even somewhat above the corner frequency of the amplifier, which means a low-frequency hybrid-pi model is accurate for determining vD / vG. This evaluation is Miller's approximation[1] and provides the estimate (just set the capacitances to zero in Figure 5):


so the Miller capacitance is


The gain gm (rO//RL) is large for large RL, so even a small parasitic capacitance Cgd can become a large influence in the frequency response of the amplifier, and many circuit tricks are used to counteract this effect. One trick is to add a common-gate (current-follower) stage to make a cascode circuit. The current-follower stage presents a load to the common-source stage that is very small, namely the input resistance of the current follower (RL ≈ 1 / gm ≈ Vov / (2ID) ; see common gate). Small RL reduces CM[2]. The article on the common-emitter amplifier discusses other solutions to this problem.

Returning to Figure 5, the gate voltage is related to the input signal by voltage division as:



The bandwidth (also called the 3dB frequency) is the frequency where the signal drops to 1/ √ 2 of its low-frequency value. (In decibels, dB(√ 2) = 3.01 dB). A reduction to 1/ √ 2 occurs when ωCM RA = 1, making the input signal at this value of ω (call this value ω3dB, say) vG = VA / (1+j). The magnitude of (1+j) = √ 2. As a result the 3dB frequency f3dB = ω3dB / (2π) is:


If the parasitic gate-to-source capacitance Cgs is included in the analysis, it simply is parallel with CM, so


Notice that f3dB becomes large if the source resistance RA is small, so the Miller amplification of the capacitance has little effect upon the bandwidth for small RA. This observation suggests another circuit trick to increase bandwidth: add a common-drain (voltage-follower) stage between the driver and the common-source stage so the Thévenin resistance of the combined driver plus voltage follower is less than the RA of the original driver.

Examination of the output side of the circuit in Figure 2 enables the frequency dependence of the gain vD / vG to be found, providing a check that the low-frequency evaluation of the Miller capacitance is adequate for frequencies f even larger than f3dB. (See article on pole splitting to see how the output side of the circuit is handled.)


Figure 3: Basic N-channel MOSFET common-source amplifier with active load ID.


Figure 4: Small-signal circuit for N-channel MOSFET common-source amplifier.


Figure 5: Small-signal circuit for N-channel MOSFET common-source amplifier using Miller's theorem to introduce Miller capacitance CM.

YOSEPH L. BUITRAGO L.
C.I. 18.257.871
EES. SECCION 2

JFET Amplifier

So far we have looked at the Bipolar type amplifiers and especially the Common Emitter amplifier, but small signal amplifiers can also be made using Field Effect Transistors or FET's. These devices have the advantage over bipolar devices of having an extremely high input impedance along with a low noise output making them very useful in amplifier circuits using very small signals. The design of an amplifier circuit based around a JFET (n-channel FET for this example) or even a MOSFET is exactly the same principle as that for a bipolar device and for a Class A amplifier as we looked at in the previous tutorial. A suitable Quiescent point still needs to be found for the correct biasing of the amplifier circuit with amplifier configurations of Common Source, Common Drain and Common Gate available for FET devices. In this tutorial we will look at the JFET Amplifier as a common source amplifier as this is the most widely used design. Consider the Common Source JFET Amplifier circuit below.

Common Source JFET Amplifier


The circuit consists of an N-channel JFET, but the device could also be an equivalent N-channel Depletion-mode MOSFET as the circuit diagram would be the same, just a change in the FET. The JFET Gate voltage Vg is biased through the potential divider network set up by resistors R1 and R2 and is biased to operate within its saturation region which is equivalent to the active region of the BJT. The Gate biasing voltage Vg is given as:


Note that this equation only determines the ratio of the resistors R1 and R2, but in order to take advantage of the very high input impedance of the JFET as well as reducing the power dissipation within the circuit, we need to make these resistor values as high as possible, with values in the order of 1 to 10MΩ being common.

The input signal, (Vin) is applied between the Gate terminal and 0v with the Drain circuit containing the load resistor, Rd. The output voltage, Vout is developed across this load resistance. There is also an additional resistor, Rs included in the Source lead and the same Drain current also flows through this resistor. When the JFET is switched fully "ON" a voltage drop equal to Rs x Id is developed across this resistor raising the potential of the Source terminal above 0v or ground level. This voltage drop across Rs due to the Drain current provides the necessary reverse biasing condition across the Gate resistor, R2. In order to keep the Gate-source junction reverse biased, the Source voltage, Vs needs to be higher than the gate voltage, Vg. This Source voltage is therefore given as:



Then the Drain current, Id is also equal to the Source current, Is as "No Current" enters the Gate terminal and this can be given as


This potential divider biasing circuit improves the stability of the common source JFET circuit when being fed from a single DC supply compared to that of a fixed voltage biasing circuit. Both Resistor, Rs and Capacitor, Cs serve basically the same function as the Emitter resistor and capacitor in the Common Emitter Bipolar Transistor amplifier circuit, namely to provide good stability and prevent a reduction in the signal gain. However, the price paid for a stabilized quiescent Gate voltage is that more of the supply voltage is dropped across Rs.

The basic circuit and characteristics of a common source JFET amplifier are very similar to that of the Common Emitter amplifier. A DC load line is constructed by joining the two points relating to the Drain current, Id and the supply voltage, Vdd intersecting the curves at the Q-point as follows.

JFET Amplifier Characteristics Curves


As with the Common Emitter circuit, the DC load line produces a straight line equation whose gradient is given as: -1/(Rd + Rs) and that it crosses the vertical Id axis at a point equal to Vdd/(Rd + Rs). The other end of the load line crosses the horizontal axis at a point equal to Vdd. The actual position of the Q-point on the DC load line is determined by the mean value of Vg which is biased negatively as the JFET as a depletion-mode device. Like the bipolar common emitter amplifier the output of the Common Source JFET Amplifier is 1800 out of phase with the input signal.

One of the main disadvantages of using Depletion-mode JFET is that they need to be negatively biased. Should this bias fail for any reason the Gate-source voltage may rise and become positive causing an increase in Drain current resulting in failure of the Drain voltage, Vd. Also the high channel resistance, Rds(on) of the JFET, coupled with high quiescent steady state Drain current makes these devices run hot so additional heatsink is required. However, most of the problems associated with using JFET's can be greatly reduced by using enhancement-mode MOSFET devices instead.

MOSFETs or Metal Oxide Semiconductor FET's have much higher input impedances and low channel resistances compared to the equivalent JFET. Also the biasing arrangements for MOSFETs are different and unless we bias them positively for N-channel devices and negatively for P-channel devices no Drain current will flow, then we have in effect a fail safe transistor.

YOSEPH L. BUITRAGO L.
C.I. 18.257.871
EES. SECCION 2

High Performance Silicon Nanowire Field Effect Transistors


Silicon nanowires can be prepared with single-crystal structures, diameters as small as several nanometers and controllable hole and electron doping, and thus represent powerful building blocks for nanoelectronics devices such as field effect transistors. To explore the potential limits of silicon nanowire transistors, we have examined the influence of source-drain contact thermal annealing and surface passivation on key transistor properties. Thermal annealing and passivation of oxide defects using chemical modification were found to increase the average transconductance from 45 to 800 nS and average mobility from 30 to 560 cm2/V·s with peak values of 2000 nS and 1350 cm2/V·s, respectively. The comparison of these results and other key parameters with state-of-the-art planar silicon devices shows substantial advantages for silicon nanowires. The uses of nanowires as building blocks for future nanoelectronics are discussed.
YOSEPH L. BUITRAGO L.
C.I. 18.257.871
EES. SECCION 2

Other MOSFET types

Dual gate MOSFET
The dual gate MOSFET has a tetrode configuration, where both gates control the current in the device. It is commonly used for small signal devices in radio frequency applications where the second gate is normally used for gain control or mixing and frequency conversion.

FinFET
The Finfet, see figure to right, is a double gate device, one of a number of geometries being introduced to mitigate the effects of short channels and reduce drain-induced barrier lowering.

A double-gate FinFET device

Depletion-mode MOSFETs
There are depletion-mode MOSFET devices, which are less commonly used than the standard enhancement-mode devices already described. These are MOSFET devices that are doped so that a channel exists even with zero voltage from gate to source. In order to control the channel, a negative voltage is applied to the gate (for an n-channel device), depleting the channel, which reduces the current flow through the device. In essence, the depletion-mode device is equivalent to a normally closed (on) switch, while the enhancement-mode device is equivalent to a normally open (off) switch.[1]

Due to their low noise figure in the RF region, and better gain, these devices are often preferred to bipolars in RF front-ends such as in TV sets. Depletion-mode MOSFET families include BF 960 by Siemens and BF 980 by Philips (dated 1980s), whose derivatives are still used in AGC and RF mixer front-ends

NMOS logic
n-channel MOSFETs are smaller than p-channel MOSFETs and producing only one type of MOSFET on a silicon substrate is cheaper and technically simpler. These were the driving principles in the design of NMOS logic which uses n-channel MOSFETs exclusively. However, unlike CMOS logic, NMOS logic consumes power even when no switching is taking place. With advances in technology, CMOS logic displaced NMOS logic in the 1980s to become the preferred process for digital chips.

Power MOSFET
Main article: Power MOSFET
Power MOSFETs have a different structure than the one presented above.[35] As with all power devices, the structure is vertical and not planar. Using a vertical structure, it is possible for the transistor to sustain both high blocking voltage and high current. The voltage rating of the transistor is a function of the doping and thickness of the N-epitaxial layer (see cross section), while the current rating is a function of the channel width (the wider the channel, the higher the current). In a planar structure, the current and breakdown voltage ratings are both a function of the channel dimensions (respectively width and length of the channel), resulting in inefficient use of the "silicon estate". With the vertical structure, the component area is roughly proportional to the current it can sustain, and the component thickness (actually the N-epitaxial layer thickness) is proportional to the breakdown voltage.

It is worth noting that power MOSFETs with lateral structure are mainly used in high-end audio amplifiers. Their advantage is a better behaviour in the saturated region (corresponding to the linear region of a bipolar transistor) than the vertical MOSFETs. Vertical MOSFETs are designed for switching applications.


Cross section of a Power MOSFET, with square cells. A typical transistor is constituted of several thousand cells

DMOS
DMOS stands for double-diffused metal–oxide–semiconductor. Most of the power MOSFETs are made using this technology

RHBD MOSFETs
Semiconductor sub-micron and nano-meter electronic circuits are the primary concern for operating within the normal tolerance in harsh radiation environments like space. One of the design approaches for making a radiation-hardened-by-design (RHBD) device is Enclosed-Layout-Transistor (ELT). Normally, the gate of the MOSFET surrounds the drain, which is placed in the center of the ELT. The source of the MOSFET surrounds the gate. Another RHBD MOSFET is called H-Gate. Both of these transistors have very low leakage current with respect to radiation. However, they are large in size and take more space on silicon than a standard MOSFET.

Newer technologies are emerging for smaller devices for cost saving, low power and increased operating speed. The standard MOSFET is also becoming extremely sensitive to radiation for the newer technologies. A lot more research works should be completed before space electronics can safely use RHBD MOSFET circuits of nanotechnology.

When radiation strikes near the silicon oxide region (STI) of the MOSFET, the channel inversion occurs at the corners of the standard MOSFET due to accumulation of radiation induced trapped charges. If the charges are large enough, the accumulated charges affect STI surface edges along the channel near the channel interface (gate) of the standard MOSFET. Thus the device channel inversion occurs along the channel edges and the device creates off-state leakage path, causing device to turn on. So the reliability of circuits degrades severely. The ELT offers many advantages. These advantages include improvement of reliability by reducing unwanted surface inversion at the gate edges that occurs in the standard MOSFET. Since the gate edges are enclosed in ELT, there is no gate oxide edge (STI at gate interface), and thus the transistor off-state leakage is reduced very much.

Low-power microelectronic circuits including computers, communication devices and monitoring systems in space shuttle and satellites are very different than what we use on earth. They are radiation (high-speed atomic particles like proton and neutron, solar flare magnetic energy dissipation in earth's space, energetic cosmic rays like X-ray, Gamma-ray etc.) tolerant circuits. These special electronics are designed by applying very different techniques using RHBD MOSFETs to ensure the safe space journey and also space-walk of astronauts.

YOSEPH L. BUITRAGO L.
C.I. 18.257.871
EES. SECCION 2

CMOS

Complementary metal–oxide–semiconductor (CMOS) (pronounced /ˈsiːmɒs/) is a technology for constructing integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM, and other digital logic circuits. CMOS technology is also used for several analog circuits such as image sensors, data converters, and highly integrated transceivers for many types of communication. Frank Wanlass successfully patented CMOS in 1967 (US patent 3,356,858).

CMOS is also sometimes referred to as complementary-symmetry metal–oxide–semiconductor (or COS-MOS). The words "complementary-symmetry" refer to the fact that the typical digital design style with CMOS uses complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions.

Two important characteristics of CMOS devices are high noise immunity and low static power consumption. Significant power is only drawn while the transistors in the CMOS device are switching between on and off states. Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for example transistor-transistor logic (TTL) or NMOS logic, which uses all n-channel devices without p-channel devices. CMOS also allows a high density of logic functions on a chip. It was primarily this reason why CMOS won the race in the eighties and became the most used technology to be implemented in VLSI chips.

The phrase "metal–oxide–semiconductor" is a reference to the physical structure of certain field-effect transistors, having a metal gate electrode placed on top of an oxide insulator, which in turn is on top of a semiconductor material. Aluminum was once used but now the material is polysilicon. Other metal gates have made a comeback with the advent of high-k dielectric materials in the CMOS process, as announced by IBM and Intel for the 45 nanometer node and beyond

Technical details
"CMOS" refers to both a particular style of digital circuitry design, and the family of processes used to implement that circuitry on integrated circuits (chips). CMOS circuitry dissipates less power than logic families with resistive loads. Since this advantage has increased and grown more important, CMOS processes and variants have come to dominate, thus the vast majority of modern integrated circuit manufacturing is on CMOS processes.[citation needed] As of 2010, the CPUs with the best performance per watt each year have been CMOS static logic since 1976.

CMOS circuits use a combination of p-type and n-type metal–oxide–semiconductor field-effect transistors (MOSFETs) to implement logic gates and other digital circuits found in computers, telecommunications equipment, and signal processing equipment. Although CMOS logic can be implemented with discrete devices (for instance, in an introductory circuits class), typical commercial CMOS products are integrated circuits composed of millions (or hundreds of millions) of transistors of both types on a rectangular piece of silicon of between 0.1 and 4 square centimeters.[citation needed] These devices are commonly called "chips", although within the industry they are also referred to as "die" (singular) or "dice", "dies", or "die" (plural).

Composition
The main principle behind CMOS circuits that allows them to implement logic gates is the use of p-type and n-type metal–oxide–semiconductor field-effect transistors to create paths to the output from either the voltage source or ground. When a path to output is created from the voltage source, the circuit is said to be pulled up. The other circuit state occurs when a path to output is created from ground and the output pulled down to the ground potential.
Output is inversion of input
CMOS circuits are constructed so that all PMOS transistors must have either an input from the voltage source or from another PMOS transistor. Similarly, all NMOS transistors must have either an input from ground or from another NMOS transistor. The composition of a PMOS transistor creates low resistance between its source and drain contacts when a low gate voltage is applied and high resistance when a high gate voltage is applied. On the other hand, the composition of an NMOS transistor creates high resistance between source and drain when a low gate voltage is applied and low resistance when a high gate voltage is applied.

The image on the right shows what happens when an input is connected to both a PMOS transistor (top of diagram) and an NMOS transistor (bottom of diagram). When the voltage of input A is low, the NMOS transistor's channel is in a high resistance state. This limits the current that can flow from Q to ground. The PMOS transistor's channel is in a low resistance state and much more current can flow from the supply to the output. Because the resistance between the supply voltage and Q is low, the voltage drop between the supply voltage and Q due to a current drawn from Q is small. The output therefore registers a high voltage.

On the other hand, when the voltage of input A is high, the PMOS transistor is in an off (high resistance) state so it would limit the current flowing from the positive supply to the output, while the NMOS transistor is in an on (low resistance) state, allowing the output to drain to ground. Because the resistance between Q and ground is low, the voltage drop due to a current drawn into Q placing Q above ground is small. This low drop results in the output registering a low voltage.

In short, the outputs of the PMOS and NMOS transistors are complementary such that when the input is low, the output is high, and when the input is high, the output is low. Because of this opposite behavior of input and output, the CMOS circuits' output is the inversion of the input.


Static CMOS Inverter

Duality
An important characteristic of a CMOS circuit is the duality that exists between its PMOS transistors and NMOS transistors. A CMOS circuit is created to allow a path always to exist from the output to either the power source or ground. To accomplish this, the set of all paths to the voltage source must be the complement of the set of all paths to ground. This can be easily accomplished by defining one in terms of the NOT of the other. Due to the De Morgan's laws based logic, the PMOS transistors in parallel have corresponding NMOS transistors in series while the PMOS transistors in series have corresponding NMOS transistors in parallel.

Logic
More complex logic functions such as those involving AND and OR gates require manipulating the paths between gates to represent the logic. When a path consists of two transistors in series, then both transistors must have low resistance to the corresponding supply voltage, modeling an AND. When a path consists of two transistors in parallel, then either one or both of the transistors must have low resistance to connect the supply voltage to the output, modeling an OR.

Shown on the right is a circuit diagram of a NAND gate in CMOS logic. If both of the A and B inputs are high, then both the NMOS transistors (bottom half of the diagram) will conduct, neither of the PMOS transistors (top half) will conduct, and a conductive path will be established between the output and Vss (ground), bringing the output low. If either of the A or B inputs is low, one of the NMOS transistors will not conduct, one of the PMOS transistors will, and a conductive path will be established between the output and Vdd (voltage source), bringing the output high.

An advantage of CMOS over NMOS is that both low-to-high and high-to-low output transitions are fast since the pull-up transistors have low resistance when switched on, unlike the load resistors in NMOS logic. In addition, the output signal swings the full voltage between the low and high rails. This strong, more nearly symmetric response also makes CMOS more resistant to noise.

See Logical effort for a method of calculating delay in a CMOS circuit.


NAND gate in CMOS logic

Example: NAND gate in physical layout
This example shows a NAND logic device drawn as a physical representation as it would be manufactured. The physical layout perspective is a "bird's eye view" of a stack of layers. The circuit is constructed on a P-type substrate. The polysilicon, diffusion, and n-well are referred to as "base layers" and are actually inserted into trenches of the P-type substrate. The contacts penetrate an insulating layer between the base layers and the first layer of metal (metal1) making a connection.

The inputs to the NAND (illustrated in green coloring) are in polysilicon. The CMOS transistors (devices) are formed by the intersection of the polysilicon and diffusion: N diffusion for the N device; P diffusion for the P device (illustrated in salmon and yellow coloring respectively). The output ("out") is connected together in metal (illustrated in cyan coloring). Connections between metal and polysilicon or diffusion are made through contacts (illustrated as black squares). The physical layout example matches the NAND logic circuit given in the previous example.

The N device is manufactured on a P-type substrate. The P device is manufactured in an N-type well (n-well). A P-type substrate "tap" is connected to VSS and an N-type n-well tap is connected to VDD to prevent latchup.


The physical layout of a NAND circuit. The larger regions of N-type diffusion and P-type diffusion are part of the transistors. The two smaller regions on the left are taps to prevent latchup.

Cross section of two transistor in a CMOS gate, in an N-well CMOS process‎

Power: switching and leakage
CMOS logic dissipates less power than NMOS logic circuits because CMOS dissipates power only when switching ("dynamic power"). On a typical ASIC in a modern 90 nanometer process, switching the output might take 120 picoseconds, and happen once every ten nanoseconds. NMOS logic dissipates power whenever the output is low ("static power"), because there is a current path from Vdd to Vss through the load resistor and the n-type network.

CMOS circuits dissipate power by charging the various load capacitances (mostly gate and wire capacitance, but also drain and some source capacitances) whenever they are switched. The charge moved is the capacitance multiplied by the voltage change. Multiply by the switching frequency on the load capacitances to get the current used, and multiply by voltage again to get the characteristic switching power dissipated by a CMOS device: P = CV2f.

An additional form of power consumption became significant in the 1990s as wires on chip became narrower and the long wires became more resistive. CMOS gates at the end of those resistive wires see slow input transitions. During the middle of these transitions, both the NMOS and PMOS networks are partially conductive, and current flows directly from Vdd to Vss. The power thus used is called crowbar power. Careful design which avoids weakly driven long skinny wires has ameliorated this effect, and crowbar power is nearly always substantially smaller than switching power.

Both NMOS and PMOS transistors have a gate–source threshold voltage, below which the current (called subthreshold current) through the device drops exponentially. Historically, CMOS designs operated at supply voltages much larger than their threshold voltages (Vdd might have been 5 V, and Vth for both NMOS and PMOS might have been 700 mV). A special type of the CMOS transistor with near zero threshold voltage is the native transistor.

To speed up designs, manufacturers have switched to constructions that have lower voltage thresholds;[citation needed] but because of this a modern NMOS transistor with a Vth of 200 mV has a significant subthreshold leakage current. Designs (e.g. desktop processors) which include vast numbers of circuits which are not actively switching still consume power because of this leakage current. Leakage power is a significant portion of the total power consumed by such designs. Further technology advances that use even thinner gate dielectrics have an additional leakage component because of current tunnelling through the extremely thin gate dielectric. Using high-k dielectrics instead of silicon dioxide that is the conventional gate dielectric allows similar device performance, but with a thicker gate insulator, thus avoiding this current. Leakage power reduction using new material and system design is critical to sustaining scaling of CMOS. A good overview of leakage and reduction methods are explained in the book Leakage in Nanometer CMOS Technologies ISBN 0-387-25737-3.

Analog CMOS
Besides digital applications, CMOS technology is also used in analog applications. For example, there are CMOS operational amplifier ICs available in the market. Transmission gates may be used instead of signal relays. CMOS technology is also widely used for RF circuits all the way to microwave frequencies, in mixed-signal (analog+digital) applications.

Temperature range
Conventional CMOS devices work over a range of −55 °C to +125 °C. There were theoretical indications as early as August 2008 that silicon CMOS will work down to 40 kelvins, or −233 °C. Functioning temperatures near 40 kelvins have since been achieved using overclocked AMD Phenom II processors with a combination of liquid nitrogen and liquid helium cooling

YOSEPH L. BUITRAGO L.
C.I. 18.257.871
EES. SECCION 2

MOSFET scaling

Over the past decades, the MOSFET has continually been scaled down in size; typical MOSFET channel lengths were once several micrometres, but modern integrated circuits are incorporating MOSFETs with channel lengths of tens of nanometers. Intel began production of a process featuring a 32 nm feature size (with the channel being even shorter) in late 2009. The semiconductor industry maintains a "roadmap", the ITRS, which sets the pace for MOSFET development. Historically, the difficulties with decreasing the size of the MOSFET have been associated with the semiconductor device fabrication process, the need to use very low voltages, and with poorer electrical performance necessitating circuit redesign and innovation (small MOSFETs exhibit higher leakage currents, and lower output resistance, discussed below).

Reasons for MOSFET scaling
Smaller MOSFETs are desirable for several reasons. The main reason to make transistors smaller is to pack more and more devices in a given chip area. This results in a chip with the same functionality in a smaller area, or chips with more functionality in the same area. Since fabrication costs for a semiconductor wafer are relatively fixed, the cost per integrated circuits is mainly related to the number of chips that can be produced per wafer. Hence, smaller ICs allow more chips per wafer, reducing the price per chip. In fact, over the past 30 years the number of transistors per chip has been doubled every 2–3 years once a new technology node is introduced. For example the number of MOSFETs in a microprocessor fabricated in a 45 nm technology is twice as many as in a 65 nm chip. This doubling of the transistor count was first observed by Gordon Moore in 1965 and is commonly referred to as Moore's law

It is also expected that smaller transistors switch faster. For example, one approach to size reduction is a scaling of the MOSFET that requires all device dimensions to reduce proportionally. The main device dimensions are the transistor length, width, and the oxide thickness, each (used to) scale with a factor of 0.7 per node. This way, the transistor channel resistance does not change with scaling, while gate capacitance is cut by a factor of 0.7. Hence, the RC delay of the transistor scales with a factor of 0.7.

While this has been traditionally the case for the older technologies, for the state-of-the-art MOSFETs reduction of the transistor dimensions does not necessarily translate to higher chip speed because the delay due to interconnections is more significant.



Trend of Intel CPU transistor gate length

Difficulties arising due to MOSFET size reduction
Producing MOSFETs with channel lengths much smaller than a micrometer is a challenge, and the difficulties of semiconductor device fabrication are always a limiting factor in advancing integrated circuit technology. In recent years, the small size of the MOSFET, below a few tens of nanometers, has created operational

Higher subthreshold conduction
As MOSFET geometries shrink, the voltage that can be applied to the gate must be reduced to maintain reliability. To maintain performance, the threshold voltage of the MOSFET has to be reduced as well. As threshold voltage is reduced, the transistor cannot be switched from complete turn-off to complete turn-on with the limited voltage swing available; the circuit design is a compromise between strong current in the "on" case and low current in the "off" case, and the application determines whether to favor one over the other. Subthreshold leakage (including subthreshold conduction, gate-oxide leakage and reverse-biased junction leakage), which was ignored in the past, now can consume upwards of half of the total power consumption of modern high-performance VLSI chips

Increased gate-oxide leakage
The gate oxide, which serves as insulator between the gate and channel, should be made as thin as possible to increase the channel conductivity and performance when the transistor is on and to reduce subthreshold leakage when the transistor is off. However, with current gate oxides with a thickness of around 1.2 nm (which in silicon is ~5 atoms thick) the quantum mechanical phenomenon of electron tunneling occurs between the gate and channel, leading to increased power consumption.

Insulators (referred to as high-k dielectrics) that have a larger dielectric constant than silicon dioxide, such as group IVb metal silicates e.g. hafnium and zirconium silicates and oxides are being used to reduce the gate leakage from the 45 nanometer technology node onwards. Increasing the dielectric constant of the gate dielectric allows a thicker layer while maintaining a high capacitance (capacitance is proportional to dielectric constant and inversely proportional to dielectric thickness). All else equal, a higher dielectric thickness reduces the quantum tunneling current through the dielectric between the gate and the channel. On the other hand, the barrier height of the new gate insulator is an important consideration; the difference in conduction band energy between the semiconductor and the dielectric (and the corresponding difference in valence band energy) also affects leakage current level. For the traditional gate oxide, silicon dioxide, the former barrier is approximately 8 eV. For many alternative dielectrics the value is significantly lower, tending to increase the tunneling current, somewhat negating the advantage of higher dielectric constant.

Increased junction leakage
To make devices smaller, junction design has become more complex, leading to higher doping levels, shallower junctions, "halo" doping and so forth,[27][28] all to decrease drain-induced barrier lowering (see the section on junction design). To keep these complex junctions in place, the annealing steps formerly used to remove damage and electrically active defects must be curtailed[29] increasing junction leakage. Heavier doping is also associated with thinner depletion layers and more recombination centers that result in increased leakage current, even without lattice damage.

Lower output resistance
For analog operation, good gain requires a high MOSFET output impedance, which is to say, the MOSFET current should vary only slightly with the applied drain-to-source voltage. As devices are made smaller, the influence of the drain competes more successfully with that of the gate due to the growing proximity of these two electrodes, increasing the sensitivity of the MOSFET current to the drain voltage. To counteract the resulting decrease in output resistance, circuits are made more complex, either by requiring more devices, for example the cascode and cascade amplifiers, or by feedback circuitry using operational amplifiers, for example a circuit like that in the adjacent figure.


MOSFET version of gain-boosted current mirror; M1 and M2 are in active mode, while M3 and M4 are in Ohmic mode, and act like resistors. The operational amplifier provides feedback that maintains a high output resistance

Lower transconductance
The transconductance of the MOSFET decides its gain and is proportional to hole or electron mobility (depending on device type), at least for low drain voltages. As MOSFET size is reduced, the fields in the channel increase and the dopant impurity levels increase. Both changes reduce the carrier mobility, and hence the transconductance. As channel lengths are reduced without proportional reduction in drain voltage, raising the electric field in the channel, the result is velocity saturation of the carriers, limiting the current and the transconductance.

Interconnect capacitance
Traditionally, switching time was roughly proportional to the gate capacitance of gates. However, with transistors becoming smaller and more transistors being placed on the chip, interconnect capacitance (the capacitance of the wires connecting different parts of the chip) is becoming a large percentage of capacitance.[30] [31] Signals have to travel through the interconnect, which leads to increased delay and lower performance

Heat production

Large heatsinks to cool power transistors in a TRM-800 audio amplifierThe ever-increasing density of MOSFETs on an integrated circuit creates problems of substantial localized heat generation that can impair circuit operation. Circuits operate slower at high temperatures, and have reduced reliability and shorter lifetimes. Heat sinks and other cooling methods are now required for many integrated circuits including microprocessors.

Power MOSFETs are at risk of thermal runaway. As their on-state resistance rises with temperature, if the load is approximately a constant-current load then the power loss rises correspondingly, generating further heat. When the heatsink is not able to keep the temperature low enough, the junction temperature may rise quickly and uncontrollably, resulting in destruction of the device.



Large heatsinks to cool power transistors in a TRM-800 audio amplifier

Process variations
With MOSFETS becoming smaller, the number of atoms in the silicon that produce many of the transistor's properties is becoming fewer, with the result that control of dopant numbers and placement is more erratic. During chip manufacturing, random process variations affect all transistor dimensions: length, width, junction depths, oxide thickness etc., and become a greater percentage of overall transistor size as the transistor shrinks. The transistor characteristics become less certain, more statistical. The random nature of manufacture means we do not know which particular example MOSFETs actually will end up in a particular instance of the circuit. This uncertainty forces a less optimal design because the design must work for a great variety of possible component MOSFETs. See process variation, design for manufacturability, reliability engineering, and statistical process control

Modeling challenges
Modern ICs are computer-simulated with the goal of obtaining working circuits from the very first manufactured lot. As devices are miniaturized, the complexity of the processing makes it difficult to predict exactly what the final devices look like, and modeling of physical processes becomes more challenging as well. In addition, microscopic variations in structure due simply to the probabilistic nature of atomic processes require statistical (not just deterministic) predictions. These factors combine to make adequate simulation and "right the first time" manufacture difficult.

YOSEPH L. BUITRAGO L.
C.I. 18.257.871
EES. SECCION 2

MOSFET construction

Gate material
The primary criterion for the gate material is that it is a good conductor. Highly-doped polycrystalline silicon is an acceptable but certainly not ideal conductor, and also suffers from some more technical deficiencies in its role as the standard gate material. Nevertheless, there are several reasons favoring use of polysilicon:

1.The threshold voltage (and consequently the drain to source on-current) is modified by the work function difference between the gate material and channel material. Because polysilicon is a semiconductor, its work function can be modulated by adjusting the type and level of doping. Furthermore, because polysilicon has the same bandgap as the underlying silicon channel, it is quite straightforward to tune the work function to achieve low threshold voltages for both NMOS and PMOS devices. By contrast, the work functions of metals are not easily modulated, so tuning the work function to obtain low threshold voltages becomes a significant challenge. Additionally, obtaining low-threshold devices on both PMOS and NMOS devices would likely require the use of different metals for each device type, introducing additional complexity to the fabrication process.
2.The Silicon-SiO2 interface has been well studied and is known to have relatively few defects. By contrast many metal–insulator interfaces contain significant levels of defects which can lead to Fermi-level pinning, charging, or other phenomena that ultimately degrade device performance.
3.In the MOSFET IC fabrication process, it is preferable to deposit the gate material prior to certain high-temperature steps in order to make better-performing transistors. Such high temperature steps would melt some metals, limiting the types of metal that can be used in a metal-gate-based process.
While polysilicon gates have been the de facto standard for the last twenty years, they do have some disadvantages which have led to their likely future replacement by metal gates. These disadvantages include:

1.Polysilicon is not a great conductor (approximately 1000 times more resistive than metals) which reduces the signal propagation speed through the material. The resistivity can be lowered by increasing the level of doping, but even highly doped polysilicon is not as conductive as most metals. In order to improve conductivity further, sometimes a high-temperature metal such as tungsten, titanium, cobalt, and more recently nickel is alloyed with the top layers of the polysilicon. Such a blended material is called silicide. The silicide-polysilicon combination has better electrical properties than polysilicon alone and still does not melt in subsequent processing. Also the threshold voltage is not significantly higher than with polysilicon alone, because the silicide material is not near the channel. The process in which silicide is formed on both the gate electrode and the source and drain regions is sometimes called salicide, self-aligned silicide.
2.When the transistors are extremely scaled down, it is necessary to make the gate dielectric layer very thin, around 1 nm in state-of-the-art technologies. A phenomenon observed here is the so-called poly depletion, where a depletion layer is formed in the gate polysilicon layer next to the gate dielectric when the transistor is in the inversion. To avoid this problem, a metal gate is desired. A variety of metal gates such as tantalum, tungsten, tantalum nitride, and titanium nitride are used, usually in conjunction with high-k dielectrics. An alternative is to use fully-silicided polysilicon gates, a process known as FUSI.
Insulator
As devices are made smaller, insulating layers are made thinner, and at some point tunneling of carriers through the insulator from the channel to the gate electrode takes place. To reduce the resulting leakage current, the insulator can be made thicker by choosing a material with a higher dielectric constant. To see how thickness and dielectric constant are related, note that Gauss' law connects field to charge as:



with Q = charge density, κ = dielectric constant, ε0 = permittivity of empty space and E = electric field. From this law it appears the same charge can be maintained in the channel at a lower field provided κ is increased. The voltage on the gate is given by:


with VG = gate voltage, Vch = voltage at channel side of insulator, and tins = insulator thickness. This equation shows the gate voltage will not increase when the insulator thickness increases, provided κ increases to keep tins /κ = constant (see the article on high-κ dielectrics for more detail, and the section in this article on gate-oxide leakage).

The insulator in a MOSFET is a dielectric which can in any event be silicon oxide, but many other dielectric materials are employed. The generic term for the dielectric is gate dielectric since the dielectric lies directly below the gate electrode and above the channel of the MOSFET.

Junction design
The source-to-body and drain-to-body junctions are the object of much attention because of three major factors: their design affects the current-voltage (I-V) characteristics of the device, lowering output resistance, and also the speed of the device through the loading effect of the junction capacitances, and finally, the component of stand-by power dissipation due to junction leakage.

The drain induced barrier lowering of the threshold voltage and channel length modulation effects upon I-V curves are reduced by using shallow junction extensions. In addition, halo doping can be used, that is, the addition of very thin heavily doped regions of the same doping type as the body tight against the junction walls to limit the extent of depletion regions.[33]
The capacitive effects are limited by using raised source and drain geometries that make most of the contact area border thick dielectric instead of silicon. [34]
These various features of junction design are shown (with artistic license) in the figure.
Junction leakage is discussed further in the section increased junction leakage.




MOSFET showing shallow junction extensions, raised source and drain and halo implant. Raised source and drain separated from gate by oxide spacers.

PRESENTACION DE PASOS DE CONSTRUCION DE UN FET
http://cleanroom.byu.edu/virtual_cleanroom.parts/MOSFETProcess.html

YOSEPH L. BUITRAGO L.
C.I. 18.257.871
EES. SECCION 2