JFET data sheet specifications

LF353 Wide Bandwidth Dual
JFET Input Operational Amplifier

General Description
   These devices are low cost, high speed, dual JFET input operational amplifiers with an internally trimmed input offset voltage (BI-FET IITM technology). They require low supply
current yet maintain a large gain bandwidth product and fast slew rate. In addition, well matched high voltage JFET input devices provide very low input bias and offset currents.
   The LF353 is pin compatible with the standard LM1558 allowing designers to immediately upgrade the overall performance of existing LM1558 and LM358 designs. These amplifiers may be used in applications such as high speed integrators, fast D/A converters, sample and hold circuits and many other circuits requiring low input offset voltage, low input bias current, high input impedance, high slew rate and wide bandwidth. The devices also exhibit low noise and offset voltage drift.

Features
- Internally trimmed offset voltage 10 mV
- Low input bias current 50pA
- Low input noise voltage 25 nV/0Hz
- Low input noise current 0.01 pA/0Hz
- Wide gain bandwidth 4 MHz
- High slew rate 13 V/ms
- Low supply current 3.6 mA
- High input impedance 1012X
- Low total harmonic distortion AVe10, k0.02%
RLe10k, VOe20Vpbp, BWe20 Hz-20 kHz
- Low 1/f noise corner 50 Hz
- Fast settling time to 0.01% 2 ms

Absolute Maximum Ratings
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Supply Voltage 18V
Power Dissipation (Note 1)
Operating Temperature Range 0ºC to a70ºC
Tj(MAX) 150ºC
Differential Input Voltage 30V
Input Voltage Range (Note 2) 15V
Output Short Circuit Duration Continuous
Storage Temperature Range -65ºC to +150ºC
Lead Temp. (Soldering, 10 sec.) 260ºC
Soldering Information
Dual-In-Line Package
Soldering (10 sec.) 260ºC
Small Outline Package
Vapor Phase (60 sec.) 215ºC
Infrared (15 sec.) 220ºC
See AN-450 "Surface Mounting Methods and Their Effect on Product Reliability'' for other methods of soldering surface mount devices.
ESD Tolerance (Note 7) 1700V

Application Hints
   These devices are op amps with an internally trimmed input offset voltage and JFET input devices (BI-FET II). These JFETs have large reverse breakdown voltages from gate to
source and drain eliminating the need for clamps across the inputs. Therefore, large differential input voltages can easily be accommodated without a large increase in input current.
   The maximum differential input voltage is independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the negative supply as this will
cause large currents to flow which can result in a destroyed unit.
   Exceeding the negative common-mode limit on either input will force the output to a high state, potentially causing a reversal of phase to the output. Exceeding the negative common-mode limit on both inputs will force the amplifier output to a high state. In neither case does a latch occur since raising the input back within the common-mode range again puts the input stage and thus the amplifier in a normal operating mode.
   Exceeding the positive common-mode limit on a single input will not change the phase of the output; however, if both inputs exceed the limit, the output of the amplifier will be
forced to a high state.
   The amplifiers will operate with a common-mode input voltage equal to the positive supply; however, the gain bandwidth and slew rate may be decreased in this condition.
When the negative common-mode voltage swings to within 3V of the negative supply, an increase in input offset voltage may occur.
Each amplifier is individually biased by a zener reference which allows normal circuit operation on 6V power supplies. Supply voltages less than these may result in lower gain bandwidth and slew rate. The amplifiers will drive a 2 kX load resistance to 10V over the full temperature range of 0ºC to a70ºC. If the amplifier is forced to drive heavier load currents, however, an increase in input offset voltage may occur on the negative voltage swing and finally reach an active current limit on both positive and negative swings.

Fuente: http://www.datasheetcatalog.net/es/datasheets_pdf/L/F/3/5/LF353.shtml
Asignatura: EES
Nombre: María José Nieto Cárdenas

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