**FET amplifiers**

Before we consider amplifier circuits, the biasing of a FET must be investigated.

In this treatment, an n-channel (depletion) JFET is assumed but the techniques

described are applicable equally to p-channel and to enhancement devices.

**Biasing**

Although shunt feedback biasing can be employed, the consequent reduction of

input resistance destroys one of the major assets of FETs in amplifier circuits. To

preserve a very high input resistance the following techniques may be used.

*Voltage bias*. In the basic common-source configuration of Fig. 7.8a the source is

connected directly to earth and the gate-source voltage is established by connecting

the gate via a high-valued resistor (RG) to a negative supply voltage (VGG). If the

gate leakage current (IGSS) is zero,

VGS=VGG

which is the equation of a bias line shown superimposed on the transfer characteristic

limits in Fig. 7.8b. Owing to spread of the characteristic (Vp and IDSS), the quiescent

drain current (IDS) is subject to wide variation from device to device, ranging from

IDS(min) to IDS(max) as shown. At temperatures where the voltage dropped across RG

due to IGSS is significant, the bias line equation is modified to

which introduces a further variability of bias current.

Automatic (or self) bias. As in BJT biasing, in order to aid bias stability, a resistor

R(s) can be introduced into the source lead (Fig. 7.9a). Again the gate is returned

to a voltage supply (VGG) via resistor RG.

The bias line equation is now

and is shown plotted against the transfer characteristic in Fig. 7.9b; its slope is -1/

RS. Several observations can be made. First, considering the case where VGG=0 V

and assuming IGSS=0, it is evident that, due to the finite slope of the bias line

compared with that in the voltage bias circuit, the difference between the maximum

and minimum limits of quiescent IDS is reduced. Second, for the same design value

of drain current, if VGG is taken positive and RS correspondingly increased, the

spread of bias current around its nominal value becomes smaller at the expense of

a higher voltage drop across RS. The positive gate supply voltage can be derived

by a resistive potential divider between the drain supply (VDD) and earth.

If IGSS is significant, the drain bias current is affected as shown by Equation

7.18 but for a given value of RG (which, in the case of a potential divider, is the

parallel combination of the two resistors) the effect is reduced with increasing RS.

This automatic bias circuit is preferred for biasing FETs whether n-channel or

p-channel, depletion or enhancement. For common-source operation, RS must be

capacitively decoupled otherwise the series negative feedback reduces the signal

voltage gain.

**Current sources**

Like a BJT, a FET biased in common-source behaves as a current source with a

moderately high output resistance (rds). If gate and source are connected together,

the drain current is IDSS provided that |VDS| is greater than |Vp| or |VTH|. A much

higher output resistance is achieved when an undecoupled source resistor RS is

included; in this case IDS is less than IDSS. Since in a d.c. current source circuit no

a.c. signal is applied to the gate, the gate resistor (RG) may be made a short-circuit.

Prove that the a.c. output resistance of a FET biased with an undecoupled source

resistor RS is

**Temperature stability**

JFET transfer characteristics are temperature dependent but exhibit the curious

phenomenon of a certain (IDS, VGS) point being independent of temperature.

Unfortunately this zero-temperature-coefficient bias point occurs rather close to

pinch-off where IDS and gm are usually too small to be of value.

**Common-source amplifier**

The circuit of a common-source FET amplifier is shown in Fig. 7.11a. It is left to

capacitors omitted) and to prove that

Also, rin=RG.

**Series feedback amplifier**

If series negative feedback is introduced by including an undecoupled source resistor

(RS) as shown in Fig. 7.11b, the voltage gain is reduced to

And, again, rin=RG.

In design, the gate resistor (RG) should be chosen to meet the input resistance

specification, provided that the effect of IGSS and its temperature dependence does

not unduly upset the bias conditions. In order to meet stringent bias stability and

high input resistance specifications it may be necessary to use the bootstrap bias

technique which enhances a low-valued bias resistance (for d.c.stability) into a high

a.c. signal input resistance.

**Source follower**

If the output signal is taken from the source terminal, the source-follower circuit

of Fig. 7.11c results. The voltage gain of this circuit is given by

use a high value of RS would appear to prove useful in achieving a voltage gain

close to unity. However, for a constant voltage across RS, as RS is increased so the

drain bias current must decrease and gm also decreases in sympathy. A maximum

gmRS product usually is realized for only moderate values of RS, and the voltage

gain is unlikely to exceed 0.9. The solution to this problem is to replace RS with a

high output resistance current source thus achieving a high effective resistance in

the source with a minimal d.c. voltage drop.

It can be proved that the output resistance of the source-follower is:

which, again owing to the relatively low gm of a FET, is significantly higher

than the output resistance of the emitter-follower counterpart.

The input resistance of the simple source-follower is equal to RG but bootstrap

bias techniques can raise this value.

Prove the voltage gain expressions for the common-source, series feedback and

source-follower amplifiers given in Equations 7.20, 7.22 and 7.24. Also prove that

the output resistance of a source-follower is as given in Equation 7.25.

**Differential amplifier**

Matched FETs can be used in a differential amplifier configuration to achieve a very

high a.c. input resistance (1012 ) and extremely low d.c. input currents (30 pA).

FET and bipolar technologies have been combined in BIFET operational

amplifiers, the FET input stage improving the input performance compared with

all-bipolar circuits. Operational amplifiers using only MOSTs are also available.

Fuente: "Transistor Circuit Techniques" G. J. Ritchie Third Edicion

Asignatura: EES

Nombre: María José Nieto Cárdenas

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